Three CHIPS Act-funded logic fabs reached volume production in mid-2026. TSMC's Fab 21 Phase 1 in Phoenix is producing 4-nanometer chips at 24,000 wafers per month, with Apple, AMD, and Nvidia as confirmed customers. Intel's Fab 52 in Chandler, Arizona began shipping 18A revenue wafers to paying customers including Amazon and Microsoft in the first quarter. Samsung's Taylor, Texas facility reached 15,000 wafers per month of 3-nanometer production. Combined capacity across the three facilities is approximately 69,000 wafers per month of leading-edge logic, representing roughly 8 percent of global advanced-node capacity.
The investments that produced this — $6.6 billion in CHIPS Act funding for TSMC, $8.5 billion for Intel, $4.75 billion for Samsung — are yielding measurable output. TSMC reported in May that Arizona's cost structure is tracking toward parity with Taiwan operations faster than originally projected, driven by improving workforce efficiency and locally sourced chemical supply chains.
The packaging gap
Production at the fab level is not the end of the chip manufacturing chain. Advanced chips require complex packaging — chip-on-wafer-on-substrate assembly, silicon interposers, high-bandwidth memory integration — that is almost entirely done in Taiwan and South Korea. TSMC's Arizona chips have been shipped back to Taiwan for final assembly, a round trip that undermines the domestic supply chain argument that domestic fab production is supposed to serve.
TSMC signed a $2 billion five-year partnership with GlobalFoundries in October to produce silicon interposers at GlobalFoundries' Malta, New York facility, but volume production will not begin until the first half of 2028. TSMC's own advanced packaging facility in Arizona is expected in 2028; Amkor's US CoWoS-compatible facility in 2029. The gap between domestic wafer production and domestic packaging capacity is measured in years, not months.
What the buildout means for AI
The AI infrastructure buildout has been the demand signal that justifies the investment, alongside Google's push to consolidate enterprise AI into a single agent that routes jobs between Gemini and Claude models — the compute that runs those agents has to come from somewhere. that justifies the investment. AI accelerators require more advanced packaging integration than any prior generation of chips — Nvidia's Blackwell GPUs are the clearest example — and the bottleneck to US production of those products is packaging, not wafer fab capacity. The fabs that are running can produce the die. Getting the finished product out of the domestic supply chain requires the rest of the infrastructure, most of which does not yet exist at scale in the United States.
TSMC Phase 2 in Arizona, producing 3-nanometer chips, is expected in 2027. The workforce constraint that is slowing reshoring broadly applies to semiconductor manufacturing specifically: TSMC Arizona directly employs approximately 2,200 workers, and building the supporting supplier ecosystem requires trades and technicians in the same categories that are in short supply across manufacturing sectors. Intel Ohio's full module is projected for 2030. The buildout is real. The timeline for a genuinely domestic advanced chip supply chain is the back half of the decade.
Topics technologysemiconductorsmanufacturingAI
